This application is based upon Japanese Patent Application No. Hei. 10-268945 filed on Sep. 7, 1998, the contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device and especially to a semiconductor device having a MOS (Metal Oxide Semiconductor) type transistor, and method of manufacturing the same.
2. Related Art
A MOS type transistor having an offset-gate structure has been proposed. This MOS type transistor can release an electric field concentration at an end position of a gate to enhance a drain withstand voltage by providing an offset region, which is a non-gate-forming portion, between the end position of the gate and a drain on a surface of a silicon substrate.
The offset-gate structure is formed by adopting photolithography so as to prevent the offset region from being implanted impurities as donor or acceptor, when a source and the drain are formed after forming a gate portion on the surface of the silicon substrate.
On the contrary, in order to comply with a desire for high-speed operation of a transistor, there has been known a Salicide (Self Aligned Silicide) technology that a gate, a source and a drain are changed to suicides to reduce a transistor resistance. The Salicide technology generally has the following steps. That is, after forming the gate portion, the source and the drain, a metal such as titanium (Ti) is deposited, and then surfaces of a gate electrode, the source and the drain are changed to silicides with a self-alignment.
However, when the Salicide technology is adopted to the transistor having the offset structure, part of the offset region on the surface of the silicon substrate is also changed to silicide, and accordingly, the surface of the silicon substrate is electrically conducted from the drain to the end portion of the gate via the silicide. As a result, an electric field concentration occurs at the end portion of the gate on the silicon substrate. Therefore, it is difficult to achieve a release of the electric field concentration and a lowering the transistor resistance at the same time.
This invention has been conceived in view of the background thus far described and it is an object to provide a semiconductor device, which can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time.
According to the present invention, since surfaces of a source, a drain and a gate electrode are silicides, a transistor resistance is reduced. Furthermore, since a surface of an offset region formed between the gate portion and the drain does not include silicide, it can prevent a potential of an end portion of the gate portion from being identical to a potential of the drain due to silicide, and it can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time.
According to another aspect of the present invention, a spacer covering an offset region is formed by spacer forming step. At metal deposition step, a deposited metal formed at the offset region does not contact with a silicon surface of a silicon substrate because of an existence of the spacer. Therefore, at the silicide step, surfaces of a source, a drain and a gate electrode are changed to suicides with a self-alignment, whereas and a surface of the offset region is not changed to silicide. Hence, it can manufacture a semiconductor device, which can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time.